Ein logisch-topologischer Kalkül zur Konstruktion von integrierten Schaltkreisen

Es wird ein CAD-System ICAD-IC vorgestellt, das den Entwurf integrierter Schaltungen unterstützen soll. Der Kern des Systems besteht in einem Netzkalkül, der es erlaubt, neben der logischen Information auch geometrische Informationen zu handhaben. Dieser Kalkül besitzt verschiedene Ausprägungen, die den Entwurf auf verschiedenen Entwurfsebenen unterstützen. Das System ist um den Kalkül herum entwickelt, wie etwa ALGOL um die Numerik. Soweit das System bis jetzt entwickelt ist, betrifft es die logisch-topologische Entwurfsebene und den Übergang zur topographischen Entwurfsebene. Wir stellen hier das Konzept des Kalküls vor und erläutern an Beispielen einige Grundlagenuntersuchungen zu diesem Thema.We present a CAD-system \u27CAD-IC\u27, supporting the automatic design of integrated circuits. The kernel of the system is based on a "calculus of nets", which allows both, the handling of logical and geometrical information. Depending on the design-level different versions of this calculus may be adopted. The system itself is built around this calculus, as f.e. ALGOL around numerics. As far as the system is developed at the moment, it mainly deals with the logical-topological design level and the transition to the topographical level. We give the main ideas of the calculus and illustrate some basic investigations with help of examples

9. Fachgespräch Sensornetze der GI/ITG Fachgruppe Kommunikation und Verteilte Systeme

Jährliches Fachgespräch zu Sensornetzen der GI/ITG Fachgruppe Kommunikation und Verteilte Systeme, 16. - 17. September 2010, Universität Würzbur

Optimal Technology Mapping for Single Output Cells

This paper presents a new approach to technology mapping for arbitrary technologies with single output cells. It overcomes the restrictions of tree-mappingbased methods. Optimal algorithms for special cases of DAG-mapping are presented: for minimum delay mapping and for duplication-free mapping under a class of simple cost functions (including area and delay). Heuristics for the general case and for computing AT-tradeoffs are developed and applied to LUT-based FPGAs. 1 Introduction Compiling a set of given boolean functions into an optimum hardware implementation is a very ambitious task. That is why it is usually divided into a technology independent and a technology mapping part. The former minimizes abstract cost measures as the depth and the number of literals of a factored representation [1]. The latter gets a network with nodes representing primitive functions and compiles it into a circuit using more complex cells available as parts of a given target technology. In this paper w..

TEMPLATE: A generic TEchnology Mapping PLATform

Technology mapping problems arize in logic synthesis systems, when the gap between a synthesized boolean network and the implementation of that network within a given target technology has to be bridged. This paper presents a modular, versatile technology mapping system that supports many different target technologies. Guided by a complexity analysis of the problem, we develop a variety of efficient, exact or heuristic methods for technology driven network clustering. Depending on the target technology and optimization methods and goals, different subnetworks must be provided as candidates for clustering. Methods to achieve this are also included. We conclude with experimental results we obtained with several configurations of the system for different target technologies

Matching a Boolean Function against a Set of Functions

Boolean matching tackles the problem whether a subcircuit of a boolean network can be substituted by a cell from a cell library. In previous approaches [6, 9, 7] each pair of a subcircuit and a cell is tested for NPN-equivalence. This becomes very expensive if the cell library is large. In our approach the time complexity for matching a subcircuit against a library L is almost independent of the size of L. The CPU time also remains the same for matching a subcircuit against the huge set of functions obtained by bridging and fixing cell inputs; but the use of these functions in technology mapping is very profitable. Our method is based on a canonical representative for each NPN-equivalence class. We show how this representative can be computed efficiently and how it can be used for matching a boolean function against a set of library functions

Node Normalization and Decomposition in Low Power Technology Mapping

In static CMOS technology the decomposition of the nodes of a circuit netlist can significantly reduce the overall power dissipation of the circuit. We present a normalization algorithm which extracts the largest recognizable nodes of the given structure. Then we examine a known decomposition algorithm for the normalized nodes and propose a new one which is provable optimal and tractable for moderate node size. Resulting reduction of the overall switching activity on standard benchmark circuits is shown for ROBDD computed as well as uncorrelated signal probabilities